1. Field of the Invention
The present invention relates to an information processing unit such as a central processing unit (CPU), and more particularly to an information processing unit for performing switching control of reset vector addresses at reset processing.
2. Description of Related Art
Generally speaking, a CPU clears its various types of registers such as a built-in program counter into their initial state by receiving a reset signal, and starts its operation by reading an instruction from a specified address on its memory, a reset vector address.
Conventionally, the reset vector address the CPU generates is fixed for the CPU. Specifically, the CPU has one reset vector address, and always starts its program from the same address in response to the reset signal. For example, the CPU enters a reset state when its reset terminal is placed at a low level. Subsequently, when the reset terminal is returned to a high level, the reset is released so that the CPU starts to execute the program from the reset vector address (for example, “FFFC”). More specifically, the CPU reads an instruction from the address “FFFC”, puts it into the built-in program counter, and executes the program sequentially.
However, since the conventional CPU has the fixed reset vector address, it has a problem in that it cannot reflect the condition, in which the reset takes place, onto the operation after the reset is released. For example, consider the case where hardware is faulty which is used by the program the CPU executes from the fixed reset vector address after the reset processing. When the CPU proceeds with the program from the reset vector address, and enters the reset state at the time when the program accesses the faulty hardware, the CPU executes the program that uses the faulty hardware from the same reset vector address, again. Thus, the CPU is reset at the same location, thereby iterating its operation.
To prevent the foregoing problem, some conventional techniques are proposed such as those disclosed in Japanese patent application laid-open Nos. 1-201762 and 11-31068, for example.
The conventional techniques select one of a plurality of reset vector addresses in response to a voltage level or by selecting an external pin at the reset.
FIG. 7 is a circuit diagram showing a configuration of a conventional CPU, which enables the selection of one of the plurality of reset vector addresses. In FIG. 7, the reference numeral 11 designates a CPU including a reset terminal 11a and a reset selection terminal 11b. The reference numeral 12 designates an address selection circuit connected to the reset terminal 11a and reset selection terminal 11b. 
Next, the operation of the conventional CPU will be described.
In response to a reset signal (low level) supplied to the reset terminal 11a, an inverter 12a outputs a high-level signal. In this case, when a voltage Vss (low level) is applied to the reset selection terminal 11b, the inverter 12b outputs a high-level signal, so that an AND gate 12c outputs a high-level signal. Thus, the address selection circuit 12 selects the address “FFFC”. In other words, in response to the reset signal and voltage Vss supplied to the reset terminal 11a and reset selection terminal 11b, respectively, the address selection circuit 12 selects the address “FFFC”. Then, after the reset release, the CPU 11 generates the address “FFFC” as the reset vector address, reads the instruction (for example, “C000”) from the address “FFFC”, and sets it into the program counter (not shown). Thus, the CPU 11 executes the program from “C000”.
On the other hand, when the reset selection terminal 11b is connected to a supply voltage Vcc (high-level signal), another AND gate 12d outputs a high-level signal because the inverter 12a outputs the high-level signal. Thus, the address selection circuit 12 selects an address “FF0C”. Then, after the reset is released, the CPU 11 generates the address “FF0C” as the reset vector address, reads the instruction (for example, “D000”) from the address “FF0C”, and sets it in the program counter. Thus, the CPU 11 executes the program from “D000”.
In this way, the CPU 11 selects one of the plurality of the reset vector addresses in response to the potential applied to the reset selection terminal 11b, and executes the program in accordance with the reset vector address.
With the foregoing configuration, the conventional information processing unit can select the reset vector address in response to the potential supplied to the reset selection terminal 11b. However, it has a problem in that the reset vector address to be selected can be changed by slight fluctuations in the potential at the reset terminal 11a after the switch-on. As a result, there is a problem in that a program an operator does not expect is likely to be executed.
For example, assume that the program beginning from the address “C000” is for a destination A, and the program beginning from the address “D000” is for a destination B. In this case, the execution of the program is determined by the setting at turn-on. If the potential of the reset terminal 11a fluctuates even slightly after the power-up, the reset vector address to be selected can change regardless of the potential at the reset selection terminal 11b. For example, even when the program corresponding to the destination A must be executed after the power-up, the program corresponding to the destination B can be executed because of the change of the reset vector address owing to the slight fluctuations in the potential at the reset terminal 11a. 
Furthermore, since the conventional information processing unit is configured such that it selects one of the reset vector addresses in response to the levels of the external terminals such as the reset terminal 11a and reset selection terminal 11b, it has a problem in that it cannot select the reset vector address in response to software reset.
In addition, the conventional information processing unit has another problem of being unable to select the reset vector address in response to the reset processing either at turn-on or at operation of the CPU 11.